Referring to FIG. 1, a typical computer system includes a microprocessor (10) having, among other things, a CPU (12), a load/store unit (14), and an on-board cache memory (16). The microprocessor (10) is connected to an external cache memory (17) and a main memory (18) that both hold data and program instructions to be executed by the microprocessor (10). Internally, execution of program instructions is carried out by the CPU (12). Data needed by the CPU (12) to carry out an instruction are fetched by the load/store unit (14) and loaded into internal registers (15) of the CPU (12). A memory queue (not shown) maintains a list of outstanding memory requests. The load/store unit adds requests into the memory queue and also loads registers with values from the memory queue. Upon command from the CPU (12), the load/store unit (14) searches for the data first in the fast on-board cache (16), then in external cache memory (level 2 cache) (17), and final in the slow main memory (18).
Typically, the level two cache (17) is constructed using static random access memory (SRAM), while the main memory is constructed using dynamic random access memory (DRAM). In both cases, avoiding corruption of data stored in the memories is vital to proper operation of the computer. An error in even a single bit stored in memory may be sufficient to frustrate execution of a desired instruction by the CPU. Although various error checking mechanisms exist in the prior art, these mechanisms typically introduce undesirable overhead in terms of hardware and/or processing time. In addition, the complexity of these mechanisms may add to the overall complexity and cost of the memory system.